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| IN74LV04 HEX INVERTER The IN74LV04 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT04A. The IN74LV04 provides six inverting buffers. * * * * Wide Operating Voltage: 1.0/5.5 V Optimized for Low Voltage applications: 1.0/3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low Input Current ORDERING INFORMATION IN74LV04N Plastic IN74LV04D SOIC IZ74LV04 Chip TA = -40 / 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT PIN 14 =VCC PIN 7 = GND FUNCTION TABLE Input Output A Y L H H L 1 IN74LV04 MAXIMUM RATINGS Symbol Parameter Value Unit VCC DC supply voltage (Referenced to GND) V -0.5 / +7.0 1 IIK* DC input diode current mA 20 IOK*2 DC output diode current mA 50 3 Io* DC output source or sink current mA 25 -bus driver outputs IGND DC GND current for types with mA 50 - bus driver outputs ICC DC VCC current for types with mA 50 - bus driver outputs 750 mW PD Power dissipation per package, plastic DIP+ 500 SOIC package+ Tstg Storage temperature -65 / +150 C 260 TL Lead temperature, 1.5 mm from Case for 10 C seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C *1: VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 1.0 5.5 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to 0 VCC V GND) TA Operating Temperature, All Package Types -40 +125 C ns 1000 t r, tf Input Rise and Fall Time VCC =1.2 V 0 700 VCC 0 =2.0 V 500 0 VCC =3.0 V 400 0 VCC =3.6 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. * 2 IN74LV04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Test VCC, 25C -40C / -40C / Symbol Parameter Conditions V 85C 125C min max min max min max 0.9 0.9 VIH High-Level Input 1.2 0.9 1.4 1.4 Voltage 2.0 1.4 2.1 2.1 3.0 2.1 2.5 2.5 3.6 2.5 0.3 0.3 0.3 VIL Low-Level Input 1.2 0.6 0.6 0.6 Voltage 2.0 0.9 0.9 0.9 3.0 1.1 1.1 1.1 3.6 1.0 1.0 1.2 1.1 VOH High-Level Output VI = VIL 1.9 1.9 2.0 1.92 Voltage IO = -50 A 2.9 2.9 * 2.92 VI = VIL * 2.48 - 2.34 - 2.20 IO = -6.0 A 0.1 0.1 - 0.09 VOL Low-Level Output VI = VIH 1.2 0.1 0.1 - 0.09 Voltage 2.0 IO = 50 A 0.1 0.1 - 0.09 - 0.33 0.4 0.5 VI = VIH or VIL 3.0 IO = 6.0 m Low-Level Input Leakage Current II High-Level Input Leakage Current I Quiescent Supply Current (per Package) * : VCC= (3.30.3) V IIL VI = VCC VI = 0 or VCC IO = 0 A * * -0.1 0.1 2.0 -1.0 1.0 20 -1.0 1.0 40 Unit V V V V V V A A A 3 IN74LV04 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns, VIL=0V, VIH=VCC, RL=1 k) VCC Guaranteed Limit V 25C -40C / 85C -40C / Unit Symbol Parameter 125C min max min max min max ns 100 85 70 tTHL, (tTLH) Output Transition 1.2 24 20 16 Time, Any Output 2.0 15 13 10 * (Figure 1) 150 120 90 1.2 tPHL, (tPLH) Propagation 34 28 23 Delay, Input A to 2.0 21 18 14 Output Y (Figure * 1) CI Input Capacitance 3.0 3.5 3.5 pF CPD Power Dissipation Capacitance (Per Inverter) =25, VI=0V/VCC pF consumption: 42 Used to determine the no-load dynamic power PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz) (CLVCC2fo) - sum of the outputs tHL 0.9 V1 0.1 0.9 tLH VCC V1 0.1 Input tPHL 0.9 tPLH 0.9 V1 V1 0.1 0.1 GND VCC Output Y V1 = 0.5 VCC tTHL tTLH GND Figure 1. Switching Waveforms VCC VI PULSE GENERATOR DEVICE UNDER TEST VO Termination resistance RT - should be equal to ZOUT of pulse generators RT CL RL Figure 2. Test Circuit 4 IN74LV04 CHIP PAD DIAGRAM IZ74LV04 12 13 Chip marking 25LV04 (x=0.127; y=0.580) 11 10 09 08 1.20 0.03 Y 0.228 0.111 0.111 0.111 0.111 0.293 0.477 0.786 0.970 0.970 0.970 0.970 0.855 0.619 14 07 01 02 03 04 05 06 1.35 0.03 Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol 1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 Vcc X 0.111 0.333 0.600 0.770 1.006 1.138 1.138 1.138 1.006 0.771 0.600 0.332 0.111 0.111 5 |
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